Journal Title：Ieee Computer Architecture Letters

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

IEEE 計算機體系結(jié)構(gòu)快報是一個經(jīng)過嚴(yán)格同行評審的論壇，用于發(fā)布單處理器和多處理器計算機系統(tǒng)、計算機體系結(jié)構(gòu)、微體系結(jié)構(gòu)、工作負(fù)載特性、性能評估和模擬技術(shù)以及功耗感知計算等領(lǐng)域的早期高影響力成果。歡迎提交有關(guān)計算機體系結(jié)構(gòu)的任何主題的論文，特別是（但不限于）：微處理器和多處理器系統(tǒng)、微體系結(jié)構(gòu)和 ILP 處理器、工作負(fù)載特性、性能評估和模擬技術(shù)、編譯器硬件和操作系統(tǒng)硬件交互、互連體系結(jié)構(gòu)、內(nèi)存和緩存系統(tǒng)、體系結(jié)構(gòu)級別的功耗和散熱問題、I/O 體系結(jié)構(gòu)和技術(shù)、對先前發(fā)布結(jié)果的獨立驗證、對不成功技術(shù)的分析、特定領(lǐng)域的處理器體系結(jié)構(gòu)（例如嵌入式、圖形、網(wǎng)絡(luò)等）、實時和高可用性體系結(jié)構(gòu)、可重構(gòu)系統(tǒng)。

Ieee Computer Architecture Letters創(chuàng)刊于2002年，由Institute of Electrical and Electronics Engineers Inc.出版商出版，收稿方向涵蓋COMPUTER SCIENCE, HARDWARE & ARCHITECTURE全領(lǐng)域，此刊是中等級別的SCI期刊，所以過審相對來講不是特別難，但是該刊專業(yè)認(rèn)可度不錯，仍然是一本值得選擇的SCI期刊 。平均審稿速度 12周，或約稿 ，影響因子指數(shù)1.4，該期刊近期沒有被列入國際期刊預(yù)警名單，廣大學(xué)者值得一試。